The present invention relates generally to FIFO control logic, and more specifically relates to FIFO control logic which is configured to avoid forwarding unwanted data to the DMA.
DMA (Direct Memory Access) is a technique for transferring data from main memory to a device without passing it through a CPU. This is useful, for example, for making quick backups and for real-time applications. Generally, computers that have DMA channels can transfer data to and from devices much more quickly than computers which do not have DMA channels.
While a circuit-switching protocol is ideal when data must be transmitted quickly and must arrive in the same order in which the data is sent (such as with live audio and video), packet-switching is more efficient and robust for data that can withstand some delays in transmission, such as e-mail messages and Web pages. In a packet-switching protocol, a message is divided into packets, and the packets are sent to the destination. A packet typically contains the destination address in addition to the data. Each packet is transmitted individually and can even follow different routes to its destination. Once all the packets forming a message arrive at the destination, they are recompiled into the original message. Many modern Wide Area Network (WAN) protocols, including TCP/IP, X.25, and Frame Relay, are based on packet-switching technologies.
To have fast and efficient data transfer, it is important not to waste DMA bandwidth. However, in the prior art, FIFO control logic is configured to forward all data that is received to the DMA. Hence, in some cases, unwanted data is forwarded to the DMA, and DMA bandwidth is wasted. Additionally, because all packets which are received by the FIFO are forwarded to the DMA, the FIFO is likely to overflow.
It is an object of an embodiment of the present invention to provide a system which is configured to prevent the forwarding of unwanted data to a DMA, thereby optimizing DMA bandwidth.
Another object of an embodiment of the present invention is to provide a system which avoids the unnecessary overflow of a FIFO.
Still another object of an embodiment of the present invention is to provide a system which employs data-burst-count control logic to manage a FIFO, such that discarded packets in the FIFO are not forwarded to a DMA.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a system which includes a DMA (Direct Memory Access) interface and a MAC (Media Access Control) interface. A data FIFO and data burst information FIFO are disposed between the DMA interface and the MAC interface, and the system is configured to provide that information contained in the data burst information FIFO is used to discard unwanted data contained in the data FIFO, such that the unwanted data does not forward to the DMA interface. As such, DMA bandwidth is optimized and overflow is prevented.